RE: [coldfire-gnu-discuss] MCF547X/8X cache vs TAS instruction.

["Mike Hench" <mhench@xxxxxxxxxxxx>]

Search for the words "once per instruction" in the reference manual
As in interrupts are sampled once per instruction
It is mentioned in multiple places.
Truth is I am assuming that once is between instructions.

-----Original Message-----
From: 42Bastian [mailto:list-bastian.schick@xxxxxxxxxxx] 
Sent: Thursday, May 28, 2009 11:30 PM
To: Mike Hench; coldfire-gnu-discuss@xxxxxxxxxxxxxxxx
Subject: Re: [coldfire-gnu-discuss] MCF547X/8X cache vs TAS instruction.

Mike
> 
> 'bset' does a very similar thing however it is not SMP safe

Just out of curiosity: How can you be sure "bset" cannot be interrupted?
Do you have a reference ?

-- 
42Bastian