Re: [arm-gnu] Fwd: Issue when compiling assembly code in GCC 4.4.1 for ARM(inline issue)

[Paul Brook <paul@xxxxxxxxxxxxxxxx>]

> We are looking at an issue related to failure of arm-gcc  ( version
> 4.4.1 )   in generating correct
> assembly from inlined-asm code.
> 
> The corresponding iniline-asm is
> "   strex %2, %3, [%0];"
> 
> Its compilation fails as strex cannot have same register as first 2
> operands.
>
> /tmp/ccnJX1l7.s: Assembler messages:
> /tmp/ccnJX1l7.s:36: Error: registers may not be the same -- `strex
> r3,r3,[r2]'
> 
> Operand %2 is specified as output and %3 is  specified as input.
>
> Compilation does pass if we also specify %2 with the additional
> constraint &  .That is     "=&r"(t)
>
> Is gcc not smart enough to recognise that strex cannot use same
> register for both
> operands ?   

This is a bug in your code.  The GCC inline assembly statements are 
specifically designed to allow use of instructions/sequences that the compiler 
does not understand.  To the compiler it is just a text string.  You must 
ensure that the semantics of the inline assembly are correctly described by 
the operands.

In this case you need to use an early clobber ("&") constraint to tell the 
compiler that the input and output may not overlap.

>        :"+r"(p), "=r"(o), "=r"(t)
>        :"r"(v)
>        :"cc", "memory"

Same here. Unless told otherwise, the compiler assumes that all inputs are 
read before outputs are written (i.e. it may overlap them).

Paul